Instructions
Using the Design Compiler Reference Methodology for a Top-Down Flow
===================================================================
Note:
The file names in the following instructions refer to variable names that are
defined in the dc_setup_filenames.tcl file. Default file names are assigned for
all variables. You can customize your flow by changing the names to match the
names of the files used in your flow.
复制参考文件到一个新的位置。
information for your design.
编辑common_setup.tcl，设置设计名称、搜索路径和库信息。
编辑dc_setup.tcl来自定义DC设置。
The dc_setup.tcl file is designed to work automatically with the values
provided in common_setup.tcl. Include a list of your RTL files in the
RTL_SOURCE_FILES variable. Use only file names and take advantage of the
search_path setting to keep your files portable.
dc_setup.tcl被设计成自动与common_setup.tcl中的值协同工作。在RTL_SOURCE_FILES variable包含了一系列的RTL文件。充分利用search_path，这里只需要填写文件名。
Alternatively, you can use a separate script to read the RTL files in
Design Compiler and Formality. To use this capability, select SCRIPT for the
RTL Source Format option when you download the scripts in RMgen. The
${DCRM_RTL_READ_SCRIPT} and ${FMRM_RTL_READ_SCRIPT} variables in the
dc_setup_filenames.tcl file define the names of these scripts.
此外，你也可以使用一个分离的脚本文件在Design Compiler和Formality来读取RTL文件。在RMgen下载脚本文件时选择SCRIPT for the RTL Source Format选项来启用这一功能。dc_setup_filenames.tcl文件中的${DCRM_RTL_READ_SCRIPT}秋${FMRM_RTL_READ_SCRIPT}定义了这两个文件的名称。
Set up multicore optimization, if desired, by using the “set_host_options”
command. Ensure that you have sufficient cores and sufficient copies
of all feature licenses to support your settings.
通过”set_host_options”命令设置多核优化。确保有足够多的核和licence。
Point to a common “alib_library_analysis_path” to save some runtime in
subsequent DC sessions.
“alib_library_analysis_path”指向一个中心缓存位置，可以节省运行时间。
design synthesis.
编辑dc.tcl来自定义设计综合时要执行的步骤。
Read through this script carefully, note the comments, and choose which
steps you want to include in your synthesis. Remember that this is a
reference example and requires modification to work with your design.
仔细阅读脚本文件，注意注释，选择你综合时所需要的步骤。记住，这是一个参考例子，需要修改以适应你的设计。
You can customize the file names for input files, output files, and reports
by changing the file names in dc_setup_filenames.tcl.
你可以在dc_setup_filenames.tcl自定义输入文件、输出文件和报告的名称。
in the flow. These files are picked up automatically from the search path
defined in common_setup.tcl
确保你在此流程中有必要的设计指定的输入文件。这些文件由common_setup.tcl所定义的search path自动挑选出来。
The minimum recommended files are
至少包括：
o ${DCRM_CONSTRAINTS_INPUT_FILE} (Logical design constraints) 逻辑设计约束
o ${DCRM_DCT_DEF_INPUT_FILE} or ${DCRM_DCT_FLOORPLAN_INPUT_FILE}
(floorplan to use for topographical mode synthesis) topo模式所需要的floorplan
o ${DCRM_DFT_SIGNAL_SETUP_INPUT_FILE} (DFT signal definitions) DFT信号定义
For a complete list of expected input files, see the list at the end
of this README file.
所期望的全部输入文件，察看README文件末尾的列表。
additional minimum recommended files:
对于多电压流程，确保你至少有以下所需文件
o ${DCRM_MV_UPF_INPUT_FILE} (UPF setup file)
o ${DCRM_MV_SET_VOLTAGE_INPUT_FILE} (set_voltage commands)
o ${DCRM_MV_DCT_VOLTAGE_AREA_INPUT_FILE} (create_voltage_area commands
for topographical mode synthesis)
The dc.upf file shows a general example of a UPF file.
You can also use a Tcl-based utility, UPFgen, to quickly generate
a UPF template for your design.
For more information about UPFgen, please see the following SolvNet article:
https://solvnet.synopsys.com/retrieve/025029.html
使用dc.tcl来运行你的综合。
For the standard reference methodology flow, run the tool from the directory
above the rm_setup directory.
从rm_setup文件夹的上一级运行工具。
% dc_shell -topographical_mode -f rm_dc_scripts/dc.tcl | tee dc.log
For the Lynx-compatible reference methodology flow, run the tool from a
directory tree that is parallel to the working directory. The working directory
name should be $rm_root/rm_dc/tmp, and the directory $rm_root/rm_dc/logs should
also exist before you run the tool.
% dc_shell -topographical_mode \
-f ../../scripts_block/rm_dc_scripts/dc.tcl | tee ../logs/dc.log
reports created in the ${REPORTS} directory.
看日志和报告来验证综合结果。
When you are satisfied that synthesis completed successfully, proceed to
Formality verification in the next step.
如果对综合结果满意，执行下一步的Formality verification。
编辑fm.tcl文件。
to retention registers, you need to replace the technology library
models of those cells with Verilog simulation models for Formality
verification.
Please see the following SolvNet article for details:
https://solvnet.synopsys.com/retrieve/024106.html
通过fm.tcl来执行Formality verification。
For the standard reference methodology flow, run the tool from the directory
above the rm_setup directory.
% fm_shell -f rm_dc_scripts/fm.tcl | tee fm.log
For the Lynx-compatible reference methodology flow, run the tool from a
directory tree that is parallel to the working directory.
% fm_shell -f ../../scripts_block/rm_dc_scripts/fm.tcl | tee ../logs/fm.log
Input Files for the Design Compiler Reference Methodology
=========================================================
Note:
Not all of these files are required. You can see the complete list of input files
and define the file names in the dc_setup_filenames.tcl file.
* ${RTL_SOURCE_FILES} (list of RTL source files defined in dc_setup.tcl)
* ${DCRM_RTL_READ_SCRIPT} and ${FMRM_RTL_READ_SCRIPT} (RTL read scripts)
* ${DCRM_CONSTRAINTS_INPUT_FILE} (logical design constraints for synthesis,
top-level in hierarchical flow)
* ${DCRM_SDC_INPUT_FILE} (SDC logical design constraints,
blocks in hierarchical flow)
* ${DESIGN_NAME}.saif (Activity Interchange Format (SAIF) file for gate-level
power optimization)
* ${DCRM_DCT_DEF_INPUT_FILE} or ${DCRM_DCT_FLOORPLAN_INPUT_FILE}
(DEF floorplan to use for topographical mode synthesis)
* ${DCRM_DFT_SIGNAL_SETUP_INPUT_FILE} (DFT signal definitions)
* ${DCRM_DFT_AUTOFIX_CONFIG_INPUT_FILE} (DFT AutoFix configuration)
* ${DCRM_DFT_OCC_CONFIG_INPUT_FILE} (DFT on-chip clocking configuration)
* ${DESIGN_NAME}.upf (UPF setup file for multivoltage flow)
* ${DCRM_MV_UPF_INPUT_FILE} (set_voltage commands for multivoltage flow)
* ${DCRM_MV_DCT_VOLTAGE_AREA_INPUT_FILE} (create_voltage_area commands for
multivoltage flow)
Output Files from the Design Compiler Reference Methodology
===========================================================
The ${REPORTS} directory defined in dc_setup.tcl contains reports from the
synthesis run.
The ${RESULTS} directory defined in dc_setup.tcl contains the synthesis
output files, including the mapped netlist and the files needed for timing
analysis, power analysis, and formal verification.
You can see the complete list of output files and define the file names in
the dc_setup_filenames.tcl file.
The output files generated by the Design Compiler Reference Methodology
scripts are designed to be used as inputs for the IC Compiler Reference
Methodology. The IC Compiler Reference Methodology is the next step in the
reference flow and is available as a separate download from SolvNet.
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